1. Field of the Invention
The invention relates to the general field of semiconductor integrated circuits, more particularly to the salicide process.
2. Description of the Prior Art
Field Effect Transistors (FETs), in their simplest form, comprise a body of semiconducting material, usually silicon, having two regions of opposite conductivity type to its own, embedded within it and spaced a short distance apart. Said regions of opposite conductivity type are referred to as source and drain regions, the region between them being referred to as the gate region. In most FET designs the surface of the silicon in the gate region is covered with a thin layer of silicon oxide. Electrically separate electrodes contact all three regions.
Normally, when voltage is applied between source and drain, very little current flows since one of the two PN junctions (relative to the silicon body) will always be back biassed. When, however, voltage of the right polarity is applied to the gate the concentration of minority carriers in a thin layer immediately beneath the gate oxide can be increased to a level sufficient for it to assume the same conductivity type as the source and drain regions, thereby allowing current to flow between them.
FETs operate most efficiently if the area of the interface between source/drain and gate region is kept as small as possible and, additionally, if the resistivity of the source/drain regions at said interface is as high as possible. However, this requirement conflicts with the requirement that any series resistance introduced into the basic FET circuit by the source and drain must be kept as low as possible.
These two conflicting sets of requirements have been largely reconciled in the Lightly Doped Drain (LDD) design which is illustrated in FIG. 1 as a schematic cross-section. Source and drain regions 13 and 14, respectively, are embedded within silicon body 11, separated from one another by gate region 15. For an NPN FET design, body 11 will be P type while regions 13 and 14 are of type N+, i.e. low resistivity, satisfying the requirement that they introduce minimum series resistance into the circuit. To satisfy the requirement of high resistivity and small area at the interface with region 15, shallow layers 17 of type N-, i.e. high resistivity, extend outward a short distance from regions 13 and 14 to form the source/drain interface with gate region 15.
Since FIG. I is not drawn to scale, it does not bring out the fact that the dimensions of the various regions are very small. Furthermore, it is essential that regions 13, 14, and 17 all be very precisely located relative to one another. Also, regions 13 and 14 as well as the top surface of oxide layer 16 must all be fully covered by suitable electrical contacts that do not accidentally connect (short circuit) to one another.
These latter requirements are met by use of the Self Aligned Silicide (Salicide) process. Initially a body of silicon is provided that includes field isolation regions of thick oxide, such as 12 in FIG. 1. The entire body is then coated with a thin layer of oxide (such as 16) followed by a layer of polycrystalline silicon (poly) such as 18 in FIG. 1. Trenches 20 are then etched in layers 18 and 16 down to the level of the silicon body, leaving a pedestal of material above gate region 15. The entire structure is now subjected to an ion implantation process to produce a shallow, lightly doped layer at the bottom of trenches 20.
A layer of silicon oxide is then formed on the vertical side walls of trenches 20 to form spacers 9 and 19 and the structure is subjected to a second ion implantation process, to form the relatively deep, heavily doped, layers 13 and 14. Region 17 is now all that is left of the previously formed lightly doped layer. The structure of FIG. 1 has now been achieved.
To complete the process of making full, but non touching, contacts to the source, drain, and gate regions, spacers 9, i.e. the spacers that cover the walls of trenches 20 on the far side from gate region 15, are selectively removed, leaving spacers 19 in place. Then, a layer of a refractory metal is deposited over the entire structure, giving it the appearance illustrated in FIG. 2, where said refractory metal is represented by layer 21. The structure shown in FIG. 2 is now subjected to a heat treatment of sufficient intensity to cause layer 21 to react with underlying poly layer 18 and be fully converted to a silicide.
Finally, a selective etch treatment is used to remove any unreacted (non-silicided) refractory metal from the structure, in particular those portions of layer 21 that were in contact with spacers 19, rather than poly layer 18. The salicide process is now complete and the structure has the appearance illustrated in FIG. 3 where the layer of metal silicide is designated as 22. Source and drain regions 13 and 14, as well as the gate region 15, are now fully contacted without said contacts touching one another.
A serious limitation is associated with the above described process. Referring once again to FIG. 3, it can be seen that silicide layer 22 overlies that part of the the shallow, lightly doped, source/drain region that extends in a direction away from gate region 15 (designated here as 7 to distinguish it from the portion 17 that extends to the edge of the gate region. Because said layer is so very thin, there exists a finite probability that layer 22 may, on occasion, penetrate it and be short circuited to the main body 11.
A number of issued patents describe various apsects of and refinements to the salicide process but none, of which we are aware, addresses the above discussed problem of potential shorting through the lightly doped shallow layer. For example, Matsuoka (U.S. Pat. No. 5,053,349 Oct. 1, 1991) teaches several ways to use a refractory metal layer to connect a poly layer to the source, drain, and gate regions. With tungsten this is achieved by means of a deposition technique that causes metal to be selectively deposited on poly but not on oxide (spacers). With titanium a similar result is achieved by forming the silicide and then selectively etching. In this invention, the FET design is not of the LDD type and source/drain regions are formed through diffusion rather than ion implantation.
Koler et al. (U.S. Pat. No. 5,162,259 Nov. 10, 1992) teach a method for forming a buried contact by using a layer of heavily doped poly as a diffusion source. Dopant diffuses through a metal silicide layer into the underlying silicon substrate, thereby forming a buried contact. The preferred metal for siliciding is cobalt.
Wei et al. (U.S. Pat. No. 5,278,098 Jan. 11, 1994) teaches a fairly specific method for making contact between two coplanar layers by means of a refractory metal bridge between them, including an annealing step to form the silicide, while Wei (U.S. Pat. No. 5,346,860 Sep. 13, 1994) is similar in concept but more general.